SMSC DS LPC47M192

Rev. 07/25/2002

PRELIMINARY

LPC47M192

LPC Super I/O with Hardware Monitoring Block

FEATURES

3.3 Volt Operation (SIO Block is 5 Volt Tolerant)

LPC Interface

ACPI 1.0/2.0 Compliant

Fan Control
-

Fan Speed Control Outputs (2)

Fan Tachometer Inputs (2)

Programmable Wake-up Event Interface

PC98, PC99, PC01 Compliant

Dual Game Port Interface

MPU-401 MIDI Support

General Purpose Input/Output Pins (37)

ISA Plug-and-Play Compatible Register Set

Intelligent Auto Power Management

System Management Interrupt

2.88MB Super I/O Floppy Disk Controller

Licensed CMOS 765B Floppy Disk

Controller

Software and Register Compatible with

SMSC's Proprietary 82077AA

Compatible Core

Supports Two Floppy Drives

Configurable Open Drain/Push-Pull Output
Drivers

Supports Vertical Recording Format

16-Byte Data FIFO

100% IBM Compatibility

Detects All Overrun and Underrun

Conditions

Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption

DMA Enable Logic

Data Rate and Drive Control Registers

480 Address, Up to 15 IRQ and Three

DMA Options

Enhanced Digital Data Separator
-

2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbps Data Rates

Programmable Precompensation Modes

Keyboard Controller

8042 Software Compatible

8 Bit Microcomputer

2k Bytes of Program ROM

256 Bytes of Data RAM

Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface

Asynchronous Access to Two Data
Registers and One Status Register

Supports Interrupt and Polling Access

8 Bit Counter Timer

Port 92 Support

Fast Gate A20 and KRESET Outputs

Serial Ports
-

Two Full Function Serial Ports

High Speed 16C550A Compatible UARTs
with Send/Receive 16-Byte FIFOs

Supports 230k and 460k Baud

Programmable Baud Rate Generator

Modem Control Circuitry

480 Address and 15 IRQ Options

Infrared Port

Multiprotocol Infrared Interface

IrDA 1.0 Compliant

SHARP ASK IR

480 Addresses, Up to 15 IRQ

Multi-Mode Parallel Port with ChiProtect

Standard Mode IBM PC/XT, PC/AT, and

PS/2 Compatible Bi-directional Parallel Port

Enhanced Parallel Port (EPP) Compatible -
EPP 1.7 and EPP 1.9 (IEEE 1284
Compliant)

IEEE 1284 Compliant Enhanced Capabilities

Port (ECP)

ChiProtect Circuitry for Protection

960 Address, Up to 15 IRQ and Three DMA
Options

LPC Interface

Multiplexed Command, Address and Data
Bus

Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems

PME Interface

Hardware Monitor
-

Monitor Power supplies (+2.5V, +3.3V, +5V,
+12V, +1.8V, +1.5V, Vccp (processor
voltage), and VCC or HVSB)

Remote Thermal Diode Sensing for Two

External Temperature Measurements

Internal Ambient Temperature Measurement

Limit Comparison of all Monitored Values

System Management Bus (SMBus) Interface

THERM# Pin for out-of-limit Temperature or

Voltage Indication

RESET# Pin for generating 20msec Low
Reset Pulse

Configurable offset for internal or external
temperature channels.

AMI Keyboard BIOS ROM

128 Pin QFP, 3.2mm footprint Package

SMSC DS LPC47M192

Page 2

Rev. 07/25/2002

PRELIMINARY

80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123

Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems
Corporation. Product nam es and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are
included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given.
Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to

make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest
specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices
described any licenses under the patent rights of SMSC or ot hers. All sales are expressly conditional on your agreement to the terms and conditions of

the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement").
The product may cont ain design defects or errors known as anomalies which may cause the product's functions to deviate from published
specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life
support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses

without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this
document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITH OUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL
WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQU ENTIAL DAMAGES,

OR FOR LOST DATA, PR OFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGL IGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREAC H OF WARRANTY, OR OTHERWISE; WHETHER OR
NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE

POSSIBILITY OF SUCH DAMAGES.

SMSC DS LPC47M192

Page 3

Rev. 07/25/2002

PRELIMINARY

1 GENERAL DESCRIPTION

The LPC47M192 is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller with an LPC
interface and Hardware Monitoring capabilities.

The LPC47M192's hardware monitoring capability includes voltage and temperature monitoring with the ability to
alert the system of out-of-limit conditions. There are 7 analog inputs for monitoring external voltages of +1.5V, +1.8V,

+2.5V, +3.3V, +5V, +12V and Vccp (core processor voltage), as well as internal monitoring of the devices own HVCC
or HVSB. The LPC47M192 includes support for monitoring two external temperatures via thermal diode inputs and an
internal sensor for measuring ambient temperature. The nTHERM pin is implemented to indicate out-of-limit
temperature and voltage conditions. The block has an ability to output 20ms low pulse via nRESET pin. The
hardware monitoring block of the LPC47M192 is accessible via the System Management Bus (SMBus).

The LPC47M192 incorporates complete legacy Super I/O functionality including an 8042 based keyboard and mouse
controller, an IEEE 1284, EPP, and ECP compatible parallel port, two serial ports that are 16C550A UART
compatible, two IrDA 1.0 infrared ports, and a floppy disk controller with SMSC's true CMOS 765B core and
enhanced digital data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT

architectures and is software and register compatible with SMSC's proprietary 82077AA core. System related
functionality, which offers flexibility to the system designer, includes an MPU-401 MIDI interface, (37) General
Purpose I/O control functions, control of two LED's, a game port interface supporting two joysticks, and fan control
using fan tachometer inputs and pulse width modulator, (PWM), outputs

The LPC47M192 is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It incorporates
sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake-up events.

The LPC47M192 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA
Channel and hardware IRQ of each logical device in the LPC47M192 may be reprogrammed through the internal

configuration registers. There are up to 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ
interface, and Three DMA channels.

The LPC47M192 does not require any external filter components and is therefore easy to use and offers lower
system costs and reduced board area.

ORDERING INFORMATION

PART#

PACKAGE

KEYBOARD BIOS

LPC47M192-NC

128 Pin QFP

AMI

SMSC DS LPC47M192

Page 4

Rev. 07/25/2002

PRELIMINARY

TABLE OF CONTENTS

1 GENERAL DESCRIPTION............................................................................................................3

2 PIN LAYOUT .............................................................................................................................10

3 PIN CONFIGURATION...............................................................................................................11

4 DESCRIPTION OF PIN FUNCTIONS ..........................................................................................12

4.1 B

UFFER

AME

ESCRIPTIONS

..................................................................................................20

4.2 P

INS

HAT

EQUIRE

XTERNAL

ULLUP

ESISTORS

....................................................................20

4.2.1

Super I/O Pins.........................................................................................................................................................20

4.2.2

Hardware Monitoring Block Pins..........................................................................................................................21

5 BLOCK DIAGRAM .....................................................................................................................22

6 POWER FUNCTIONALITY .........................................................................................................23

6.1 VCC/HVCC P

OWER

...............................................................................................................23

6.1.1

3 VOLT OPERATION / 5 VOLT TOLERANCE .................................................................................................23

6.2 VREF P

.............................................................................................................................23

6.3 VTR S

UPPORT

.......................................................................................................................23

6.3.1

Trickle Power Functionality...................................................................................................................................23

6.4 32.768

RICKLE

LOCK

NPUT

...........................................................................................25

6.4.1

Indication of 32KHZ Clock ....................................................................................................................................25

6.5 I

NTERNAL

PWRGOOD............................................................................................................25

6.6 M

AXIMUM

URRENT

ALUES

....................................................................................................25

6.6.1

Super I/O Functions...............................................................................................................................................25

6.6.2

Hardware Monitoring Block Functions................................................................................................................26

6.7 P

OWER

ANAGEMENT

VENTS

(PME/SCI) ................................................................................26

7 FUNCTIONAL DESCRIPTION ....................................................................................................27

7.1 S

UPER

I/O R

EGISTERS

............................................................................................................27

7.2 H

OST

ROCESSOR

NTERFACE

(LPC) ........................................................................................27

7.3 LPC I

NTERFACE

.....................................................................................................................28

7.3.1

LPC Interface Signal Definition............................................................................................................................28

7.3.2

LPC Cycles..............................................................................................................................................................28

7.3.3

Field Definitions......................................................................................................................................................28

7.3.4

LFRAME# Usage....................................................................................................................................................28

7.3.5

I/O Read and Write Cycles...................................................................................................................................29

7.3.6

DMA Read and Write Cycles................................................................................................................................29

7.3.7

DMA Protocol..........................................................................................................................................................29

7.3.8

POWER MANAGEMENT......................................................................................................................................29

7.3.8.1

CLOCKRUN Protocol...................................................................................................................................... 29

7.3.8.2

LPCPD Protocol................................................................................................................................................ 29

7.3.9

SYNC Protocol........................................................................................................................................................29

7.3.9.1

Typical Usage ................................................................................................................................................... 29

7.3.9.2

SYNC Timeout ................................................................................................................................................. 30

7.3.9.3

SYNC Patterns and Maximum Number of SYNCS ......................................................................................... 30

7.3.9.4

SYNC Error Indication ..................................................................................................................................... 30

7.3.9.5

I/O and DMA START Fields............................................................................................................................ 30

7.3.9.6

Reset Policy....................................................................................................................................................... 30

7.3.10

LPC TRANSFERS..............................................................................................................................................30

7.3.10.1

Wait State Requirements .................................................................................................................................. 30

7.4 F

LOPPY

ISK

ONTROLLER

......................................................................................................31

7.4.1

FDC Internal Registers..........................................................................................................................................31

7.4.2

STATUS REGISTER ENCODING.......................................................................................................................41

7.4.3

Instruction Set.........................................................................................................................................................48

7.4.4

DATA TRANSFER COMMANDS ........................................................................................................................54

7.4.5

DIRECT SUPPORT FOR TWO FLOPPY DRIVES ..........................................................................................64

SMSC DS LPC47M192

Page 5

Rev. 07/25/2002

PRELIMINARY

7.4.6

FDC Swap Bit..........................................................................................................................................................64

7.5 SERIAL PORT (UART) .........................................................................................................64
7.6 INFRARED INTERFACE .......................................................................................................77
7.7 MPU-401 MIDI UART............................................................................................................78

7.7.1

Overview..................................................................................................................................................................78

7.7.2

Host Interface..........................................................................................................................................................79

7.7.3

MIDI Data Port........................................................................................................................................................79

7.7.4

Status Port...............................................................................................................................................................79

7.7.4.1

Bit 7 MIDI Receive Buffer Empty................................................................................................................. 79

7.7.4.2

Bit 6 MIDI Transmit Busy ............................................................................................................................. 80

7.7.5

MPU-401 Command Controller............................................................................................................................81

7.7.6

MIDI UART..............................................................................................................................................................82

7.7.7

MPU-401 Configuration Registers.......................................................................................................................82

7.7.7.1

Activate and I/O Base address .......................................................................................................................... 83

7.8 PARALLEL PORT.................................................................................................................83

7.8.1

IBM XT/AT Compatible, Bi-Directional and EPP Modes..................................................................................84

7.8.2

Extended Capabilities Parallel Port.....................................................................................................................88

7.9 POWER MANAGEMENT......................................................................................................98
7.10

SERIAL IRQ.................................................................................................................... 102

7.11

8042 K

EYBOARD

ONTROLLER

ESCRIPTION

........................................................................ 105

7.11.1

Keyboard Interface.......................................................................................................................................... 106

7.11.2

External Keyboard and Mouse Interface..................................................................................................... 107

7.11.3

Keyboard Power Management...................................................................................................................... 107

7.11.4

Interrupts........................................................................................................................................................... 108

7.11.5

Memory Configurations.................................................................................................................................. 108

7.11.6

Register Definitions......................................................................................................................................... 108

7.11.6.1

Host I/F Data Register .................................................................................................................................... 108

7.11.6.2

Host I/F Status Register.................................................................................................................................. 108

7.11.7

External Clock Signal...................................................................................................................................... 108

7.11.8

Default Reset Conditions............................................................................................................................... 109

7.11.9

Keyboard and Mouse PME Generation....................................................................................................... 112

7.12

GENERAL PURPOSE I/O ................................................................................................ 113

7.12.1

GPIO Pins......................................................................................................................................................... 113

7.12.2

Description........................................................................................................................................................ 114

7.12.3

GPIO Control.................................................................................................................................................... 115

7.12.4

GPIO Operation............................................................................................................................................... 116

7.12.5

GPIO PME and SMI Functionality................................................................................................................ 117

7.12.6

Either Edge Triggered Interrupts .................................................................................................................. 118

7.12.7

LED Functionality............................................................................................................................................ 118

7.13

SYSTEM MANAGEMENT INTERRUPT (SMI)................................................................... 118

7.13.1

SMI Registers................................................................................................................................................... 119

7.14

PME SUPPORT .............................................................................................................. 119

7.14.1

`Wake on Specific Key' Option...................................................................................................................... 120

7.15

FAN SPEED CONTROL AND MONITORING.................................................................... 121

7.15.1

Fan Speed Control.......................................................................................................................................... 121

7.15.2

Fan Speed Monitoring.................................................................................................................................... 122

7.16

SECURITY FEATURE ..................................................................................................... 125

7.16.1

GPIO Device Disable Register Control........................................................................................................ 125

7.16.2

Device Disable Register................................................................................................................................. 125

7.17

GAME PORT LOGIC ....................................................................................................... 125

7.17.1

Power Control Register.................................................................................................................................. 128

7.17.2

VREF Pin.......................................................................................................................................................... 128

7.18

ARDWARE

ONITORING

NTERFACE

.................................................................................... 129

7.18.1

Hardware Monitoring Interface Signal Definition........................................................................................ 129

7.18.2

SMBus Interface.............................................................................................................................................. 129

7.18.2.1

SMBus Slave Interface ................................................................................................................................... 130

7.18.3

Hardware Monitoring Block............................................................................................................................ 132

7.18.3.1

Input Monitoring............................................................................................................................................. 132

7.18.3.2

Resetting the Hardware Monitoring Block..................................................................................................... 132

7.18.3.3

Reset Out Pin.................................................................................................................................................. 133

7.18.3.4

Monitoring Modes .......................................................................................................................................... 133

7.18.3.5

Interrupt Status Registers................................................................................................................................ 134

7.18.3.6

Low Power Modes.......................................................................................................................................... 134

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